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CS4226
Surround Sound Codec
Features Description
The CS4226 is a single-chip codec providing stereo analog-to-digital and six digital-to-analog converters using delta-sigma conversion techniques. This +5 V device also contains volume control independently selectable for each of the six D/A channels. An S/PDIF receiver is included as a digital input channel. Applications include Dolby Pro-logic, THX, DTS and Dolby Digital AC-3 home theater systems, DSP based car audio systems, and other multi-channel applications. The CS4226 is packaged in a 44-pin plastic TQFP. ORDERING INFORMATION CS4226-KQ -10 to +70 C 44-pin TQFP CS4226-BQ -40 to +85 C 44-pin TQFP CDB4226 Evaluation Board
l Stereo 20-bit A/D Converters l Six 20-bit D/A Converters l S/PDIF Receiver l 108 dB DAC Signal-to-Noise Ratio (EIAJ) l Mono 20-bit A/D Converter l Programmable Input Gain & Output
-- AC-3 & MPEG Auto-detect Capability
Attenuation l On-chip Anti-aliasing and Output Smoothing Filters l De-emphasis for 32 kHz, 44.1 kHz, 48 kHz
I
SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS I2C/SPI PDN Control Port DAC#1 LRCK Digital Filters SCLK SDIN1 SDIN2 SDIN3 DAC#2 Serial Audio Data Interface DAC#3 DAC#4 DAC#5 DAC#6 Mono ADC Left ADC Right ADC Digital Filters Volume Control
VD+ VA+ Voltage Reference CMOUT AOUT1 AOUT2 Analog Low Pass and Output Stage AOUT3 AOUT4 AOUT5 AOUT6
Volume Control Volume Control Volume Control Volume Control Volume Control
SDOUT1 SDOUT2 OVL/ERR
DEM
AINAUX AIN1L MUX AIN1R AIN2L/FREQ0 AIN2R/FREQ1 DEM AIN3L/AUTODATA AIN3R/AUDIO Clock Osc/ PLL S/PDIF RX/Auxiliary Input AGND1 Divider AGND2 CLKOUT XTI XTO FILT HOLD/RUBIT LRCKAUX/RX3 RX1 DGND1 DGND2 DATAUX/RX4 SCLKAUX/RX2 Input Gain Input MUX
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved)
SEP `98 DS188F1 1
CS4226
TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS ............................................................ 3 ANALOG CHARACTERISTICS................................................................... 3 SWITCHING CHARACTERISTICS ............................................................. 5 SWITCHING CHARACTERISTICS - CONTROL PORT ............................. 6 S/PDIF RECEIVER CHARACTERISTICS................................................... 7 ABSOLUTE MAXIMUM RATINGS .............................................................. 8 RECOMMENDED OPERATING CONDITIONS .......................................... 8 DIGITAL CHARACTERISTICS.................................................................... 8 FUNCTIONAL DESCRIPTION .......................................................................... 10 Overview ................................................................................................... 10 Analog Inputs ............................................................................................ 10 Line Level Inputs ................................................................................ 10 Adjustable Input Gain ......................................................................... 11 High Pass Filter .................................................................................. 11 Analog Outputs ......................................................................................... 11 Line Level Outputs ............................................................................. 11 Output Level Attenuator ..................................................................... 11 Clock Generation ...................................................................................... 12 Clock Source ...................................................................................... 12 Master Clock Output .......................................................................... 13 Synchronization .................................................................................. 13 Digital Interfaces ....................................................................................... 13 Audio DSP Serial Interface Signals .................................................... 13 Audio DSP Serial Interface Formats .................................................. 13 Auxiliary Audio Port Signals ............................................................... 15 Auxiliary Audio Port Formats .............................................................. 15 S/PDIF Receiver ................................................................................ 15 AC-3/MPEG Auto Detection ............................................................... 16 Control Port Signals .................................................................................. 16 SPI Mode ........................................................................................... 16 I2C Mode ............................................................................................ 17 Control Port Bit Definitions ................................................................. 17 Power-up/Reset/Power Down Mode ......................................................... 18 DAC Calibration ........................................................................................ 18 De-Emphasis ............................................................................................ 18 HOLD Function ......................................................................................... 19 Power Supply, Layout, and Grounding ..................................................... 19 ADC and DAC Filter Response Plots ....................................................... 19 REGISTER DESCRIPTION ............................................................................... 21 PIN DESCRIPTION ............................................................................................ 29 PARAMETER DEFINITIONS ............................................................................. 34 PACKAGE DIMENSIONS .................................................................................. 35
Advanced product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. Dolby and AC-3 are registered trademarks, Dolby Pro-Logic is a trademark of Dolby Laboratories Licensing Corporation. DTS is a registered trademark of DTS, Inc.. THX is a registered trademark of LucasArts Entertainment Company. I2C is a registered trademark of Philips Semiconductor.
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CS4226
CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS
(TA = 25C; VA+, VD+ = +5V; Full Scale Input Sine wave, 990.52 Hz; Fs = 44.1 kHz (PLL in use); Measurement Bandwidth is 20 Hz to 20 kHz; Local components as shown in Figure 1; SPI mode, Format 3, unless otherwise specified.) CS4226-KQ Parameter Symbol Min Typ Max CS4226-BQ Min Typ Max Units
Analog Input Characteristics - Minimum gain setting (0 dB) Differential Input; unless otherwise specified. ADC Resolution Stereo Audio channels 16 20 16 20 Bits Mono channel 16 20 16 20 Bits Total Harmonic Distortion THD 0.003 0.003 % Dynamic Range (A weighted, Stereo) 92 95 90 93 dB (unweighted, Stereo) 92 90 dB (A weighted, Mono) 89 87 dB Total Harmonic -1 dB, Stereo (Note 1) THD+N -88 -82 -86 -80 dB Distortion + Noise -1 dB, Mono (Note 1) -72 -70 dB Interchannel Isolation 90 90 dB Interchannel Gain Mismatch 0.1 0.1 dB Programmable Input Gain Span 8 9 10 8 9 10 dB Gain Step Size 2.7 3 3.3 2.7 3 3.3 dB Offset Error (with high pass filter) 0 0 LSB Full Scale Input Voltage (Single Ended): 0.90 1.0 1.10 0.90 1.0 1.10 Vrms ppm/C Gain Drift 100 100 Input Resistance (Note 2) 10 10 k Input Capacitance 15 15 pF CMOUT Output Voltage 2.3 2.3 V A/D Decimation Filter Characteristics Passband (Note 3) 0.02 20.0 0.02 20.0 kHz Passband Ripple 0.01 0.01 dB 5617.2 27.56 5617.2 kHz Stopband (Note 3) 27.56 Stopband Attenuation (Note 4) 80 80 dB Group Delay (Fs = Output Sample Rate) (Note 5) tgd 15/Fs 15/Fs s s tgd 0 0 Group Delay Variation vs. Frequency
Notes: 1. Referenced to typical full-scale differential input voltage (2Vrms). 2. Input resistance is for the input selected. Non-selected inputs have a very high (>1M) input resistance. The input resistance will vary with gain value selected, but will always be greater than the min. value specified 3. Filter characteristics scale with output sample rate. 4. The analog modulator samples the input at 5.6448 MHz for an output sample rate of 44.1 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 5.6448 MHz 20.0 kHz where n = 0,1,2,3...). 5. Group delay for Fs = 44.1 kHz, tgd = 15/44.1 kHz = 340 s
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CS4226
ANALOG CHARACTERISTICS
(Continued) CS4226-KQ Min Typ Max CS4226-BQ Min Typ Max
Parameter Symbol Units High Pass Filter Characteristics Frequency Response: -3 dB (Note 3) 3.4 3.4 Hz -0.13 dB 20 20 Hz Phase Deviation @ 20 Hz (Note 3) 10 10 Deg. Passband Ripple 0 0 dB Analog Output Characteristics - Minimum Attenuation, 10 k, 100 pF load; unless otherwise specified. DAC Resolution 16 20 16 20 Bits Signal-to-Noise/Idle (DAC muted, A weighted) 101 108 99 106 dB Channel Noise Dynamic Range (DAC not muted, A weighted) 93 98 91 96 dB (DAC not muted, unweighted) 95 93 dB Total Harmonic Distortion THD 0.003 0.003 % Total Harmonic Distortion + Noise (Stereo) THD+N -88 -83 -86 -81 dB Interchannel Isolation 90 90 dB Interchannel Gain Mismatch 0.1 0.1 dB Attenuation Step Size (All Outputs) 0.7 1 1.3 0.7 1 1.3 dB Programmable Output Attenuation Span -84 -86 -84 -86 dB Offset Voltage (relative to CMOUT) 15 15 mV Full Scale Output Voltage 0.92 1.0 1.08 0.92 1.0 1.08 Vrms Gain Drift 100 100 ppm/C Out-of-Band Energy (Fs/2 to 2Fs) -60 -60 dBFs Analog Output Load Resistance: 10 10 k Capacitance: 100 100 pF Combined Digital and Analog Filter Characteristics Frequency Response 10 Hz to 20 kHz 0.1 0.1 dB Deviation from Linear Phase 0.5 0.5 Deg. Passband: to 0.01 dB corner (Notes 6, 7) 0 20.0 0 20.0 kHz Passband Ripple (Note 7) 0.01 0.01 dB Stopband (Notes 6 ,7) 24.1 24.1 kHz Stopband Attenuation (Note 8) 70 70 dB Group Delay (Fs = Input Word Rate) (Note 5) tgd 16/Fs 16/Fs s Analog Loopback Performance Signal-to-noise Ratio (CCIR-2K weighted, -20 dB input) CCIR-2K 71 71 dB Power Supply Power Supply Current Operating 90 113 90 115 mA Power Down 1 3 1 3 mA 45 45 dB Power Supply Rejection (1 kHz, 10 mVrms) Notes: 6. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz, the 0.01 dB passband edge is 0.4535xFs and the stopband edge is 0.5465xFs. 7. Digital filter characteristics. 8. Measurement bandwidth is 10 Hz to 3 Fs. 4 DS188F1
CS4226
SWITCHING CHARACTERISTICS
Parameter Audio ADC's & DAC's Sample Rate XTI Frequency XTI Pulse Width High (XTI = 256, 384, or 512 Fs) XTI = 512 Fs XTI = 384 Fs XTI = 256 Fs XTI = 512 Fs XTI = 384 Fs XTI = 256 Fs (TA = 25C; VA+, VD+ = +5V 5%, outputs loaded with 30 pF) Symbol Fs Min 4 1.024 10 21 31 10 21 31 30 (Note 9) (DSCK = 0) tdpd tlrpd (DSCK=0) (DSCK=0) tds tdh tsck (DSCK=0) tmslr 500 1------------------( 256 )Fs
Typ 500 10 50 -
Max 50 26 50 1 ------------------- + 20 ( 384 )Fs
Units kHz MHz ns ns ns ns ns ns kHz ps ns ns ns ns ns ns ns % ns ns ns ns ns
XTI Pulse Width Low
PLL Clock Recovery Frequency RX, XTI, LRCK, LRCKAUX XTI Jitter Tolerance PDN Low Time SCLK Falling Edge to SDOUT Output Valid LRCK edge to MSB valid SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge Master Mode SCLK Period SCLK Falling to LRCK Edge SCLK Duty Cycle
40 25 25 -
-
Slave Mode SCLK Period
SCLK High Time SCLK Low Time SCLK Rising to LRCK Edge LRCK Edge to SCLK Rising (DSCK=0) (DSCK=0)
tsckw tsckh tsckl tlrckd tlrcks
1------------------( 128 )Fs
40 40 20 40
Notes: 9. After powering up the CS4226, PDN should be held low until the power supply is settled.
LRCK LRCKAUX (input)
t sck SCLK* SCLKAUX* (output) t mslr LRCK LRCKAUX (output)
t lrckd
t lrcks
t sckh
t sckl
SCLK* SCLKAUX* (input)
SDIN1 SDIN2 SDIN3 DATAUX
t sckw
t lrpd t ds
t dh MSB
t dpd MSB-1
SDOUT1 SDOUT2
SDOUT1 SDOUT2
*SCLK, SCLKAUX shown for DSCK = 0 and ASCK = 0. SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively.
Audio Ports Master Mode Timing
Audio Ports Slave Mode and Data I/O timing
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CS4226
SWITCHING CHARACTERISTICS - CONTROL PORT
Inputs: logic 0 = DGND, logic 1 = VD+, CL = 30 pF) Parameter SPI Mode (SPI/I2C = 0) CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN Symbol fsck tcsh tcss tscl tsch tdsu (Note 10) tdh tpd tr1 tf1 (Note 11) (Note 11) tr2 tf2 Min 1.0 20 66 66 40 15 45 25 25 100 100 Max 6 Units MHz s ns ns ns ns ns ns ns ns ns ns (TA = 25C VD+, VA+ = 5V 5%;
Notes: 10. Data must be held for sufficient time to bridge the transition time of CCLK. 11. For FSCK < 1 MHz
CS
t css CCLK t r2 CDIN
t scl
t sch
t csh
t f2
t dsu t dh
CDOUT
t pd
6
DS188F1
CS4226
SWITCHING CHARACTERISTICS - CONTROL PORT
Inputs: logic 0 = DGND, logic 1 = VD+, CL = 30 pF) Parameter I2C(R) Mode (SPI/I2C = 1) (Note 12) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 13) SDA Setup Time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Symbol fscl tbuf thdst tlow thigh tsust thdd tsud tr tf tsusp 4.7 Min 4.7 4.0 4.7 4.0 4.7 0 250 1 300 Max 100 Units kHz s s s s s s ns s ns s (TA = 25C; VD+, VA+ = 5V 5%;
Notes: 12. I2C is a registered trademark of Philips Semiconductors. 13. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Repeated Start
Stop
SDA t buf
Start
Stop
t hdst
t high
t
hdst
tf
t susp
SCL t t t sud t sust tr
low
hdd
S/PDIF RECEIVER CHARACTERISTICS (RX1, RX2, RX3, RX4 pins only; VD+, VA+ = 5V 5%)
Parameter Input Resistance Input Voltage Input Hysteresis Input Sample Frequency CLKOUT Jitter CLKOUT Duty Cycle (high time/cycle time) (Note 14) (Note 15) Symbol ZN VTH VHYST FS Min 200 30 40 Typ 10 50 200 50 Max 50 60 Units k mVpp mV kHz ps RMS %
Notes: 14. CLKOUT Jitter is for 256xFS selected as output frequency measured from falling edge to falling edge. Jitter is greater for 384xFs and 512xFs as selected output frequency. 15. For CLKOUT frequency equal to 1xFs, 384xFs, and 512xFs. See Master Clock Output section.
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CS4226
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to 0 V.)
Parameter Power Supplies Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Digital Analog (Note 16) (Note 17) (Note 17) (Power Applied) Symbol VD+ VA+ Min -0.3 -0.3 -0.7 -0.7 -55 -65 Typ Max 6.0 6.0 10 (VA+)+0.7 (VD+)+0.7 +125 +150 Units V V mA V V C C
Notes: 16. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 17. The maximum over or under voltage is limited by the input current. Warning: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. (AGND, DGND = 0 V, all voltages with respect Min 4.75 4.75 -10 -40 Typ 5.0 5.0 25 25 Max 5.25 5.25 70 85 Units V V C C
RECOMMENDED OPERATING CONDITIONS
to 0 V.) Parameter Power Supplies |(VA+)-(VD+)|<0.4 V Operating Ambient Temperature Digital Analog CS4226-KQ CS4226-BQ
Symbol VD+ VA+ TA
DIGITAL CHARACTERISTICS (TA = 25 C; VA+, VD+ = 5 V 5%)
Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage at I0 = -2.0 mA Low-level Output Voltage at I0 = 2.0 mA Input Leakage Current Output Leakage Current (Digital Inputs) (High-Impedance Digital Outputs) (except RX1) (except RX1) Symbol VIH VIL VOH VOL Min 2.8 -0.3 (VD+)-1.0 Typ Max (VD+)+0.3 0.8 0.4 10 10 Units V V V V A A
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CS4226
Ferrite Bead +5V Supply + 1 F 2.0
0.1 F
19 VA+
+ 1 F
0.1 F
40 VD+ AOUT1 21
To Optional Input and Output Buffers
16
1 F
+
CMOUT
ANALOG FILTER
10 F
10 F From Optional Input Buffer 10 F
* 14 * 13 * 11 * 12
AOUT2 AIN1L AIN1R
22
ANALOG FILTER
CS4226
AOUT3
23
AIN2L/FREQ0
AIN2R/FREQ1
ANALOG FILTER
10 F
10 F 10 F
* 10
* 9
AOUT4
AIN3L/AUTODATA AIN3R/AUDIO AOUT5 AINAUX DEM HOLD/RUBIT RX1
24
ANALOG FILTER
25
10 F
RS RS RS 100 pF Digital Audio Source RS
* 15 27 2 42
ANALOG FILTER
AOUT6
26
ANALOG FILTER
1
DATAUX/RX4
SCL/CCLK SDA/CDOUT AD0/CS AD1/CDIN SDIN1
3 4
100 pF
RS 100 pF RS 100 pF Mode Setting RS = 50
6
5 34 RD RD RD
Microcontroller
44
LRCKAUX/RX3
43
SCLKAUX/RX2
SDIN2 SDIN3
33 32 36 35
37 38
8 7
PDN
I C/SPI SDOUT2
LRCK SCLK CLKOUT OVL/ERR
2
SDOUT1
RS RS
RS R
S
RD = 475 All unused digital inputs should be tied to DGND.
All unused analog inputs should be left floating. * Optional if analog inputs biased to within 1% of CMOUT Only needed when inputs are used for S/PDIF. Loop Current Normal High CFILT 15 nF 180 nF RFILT 43 k 3.3 k CRIP 1.5 nF 18 nF
Audio DSP
31
30
AGND1, 2 DGND1, 2 18 20 41 39
FILT 17
XTO XTI 29 R X2 ** 28
RX1 ** ** 1xFs 256, 384, 512xFs
RFILT
CFILT
C RIP
C1**
C2**
C1 C2 R X1 R X2
40 pF 40 pF 10 pF 40 pF 300 k short 10 M open
Figure 1. Recommended Connection Diagram
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CS4226
FUNCTIONAL DESCRIPTION Overview
The CS4226 has 2 channels of 20-bit analog-todigital conversion and 6 channels of 20-bit digitalto-analog conversion. A mono 20-bit ADC is also provided. All ADCs and DACs are delta-sigma converters. The stereo ADC inputs have adjustable input gain, while the DAC outputs have adjustable output attenuation. The device also contains an S/PDIF receiver capable of receiving compressed AC-3/MPEG or uncompressed digital audio data. Digital audio data for the DACs and from the ADCs is communicated over separate serial ports. This allows concurrent writing to and reading from the device. The CS4226 functions are controlled via a serial microcontroller interface. Figure 1 shows the recommended connection diagram for the CS4226.
Line In Right
100 pF
3.3 F
20 k
+
10 k
AINxR
Example Op-Amps are MC34074 or MC33078 0.47 F
5k
CMOUT
Line In Left
3.3 F
20 k
+ 10 k
AINxL
100 pF
Figure 2. Optional Line Input Buffer
ADC Control Byte. On-chip anti-aliasing filters follow the input mux providing anti-aliasing for all input channels. The analog inputs may also be configured as differential inputs. This is enabled by setting bits AIS1/0=3. In the differential configuration, the left channel inputs reside on pins 10 and 11, and the right channel inputs reside on pins 12 and 13 as described in Table 1 below. In differential mode, the full scale input level is 2 Vrms.
Single-ended AIN3L AIN3R AIN2L AIN2R AIN1L AIN1R Pin # Pin 10 Pin 9 Pin 11 Pin 12 Pin 14 Pin 13 Differential Inputs AINL+ unused AINLAINRunused AINR+
Analog Inputs Line Level Inputs
AIN1R, AIN1L, AIN2R, AIN2L, AIN3R, AIN3L and AINAUX are the line level input pins (See Figure 1). These pins are internally biased to the CMOUT voltage. A 10 F DC blocking capacitor placed in series with the input pins allows signals centered around 0 V to be input to the CS4226. Figure 2 shows an optional dual op amp buffer which combines level shifting with a gain of 0.5 to attenuate the standard line level of 2 Vrms to 1 Vrms. The CMOUT reference level is used to bias the opamps to approximately one half the supply voltage. With this input circuit, the 10 F DC blocking caps in Figure 1 may be omitted. Any remaining DC offset will be removed by the internal high-pass filters. Selection of stereo the input pair (AIN1L/R, AIN2L/R or AIN3L/R) for the 20-bit ADC's is accomplished by setting the AIS1/0 bits (ADC analog input mux control), which are accessible in the
Table 1. Single-ended vs Differential Input Pin Assignments
The analog signal is input to the mono ADC via the AINAUX pin. Independent Muting of both the stereo ADC's and the mono ADC is possible through the ADC Control Byte with the MUTR, MUTL and MUTM bits.
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CS4226
Adjustable Input Gain
The signals from the line inputs are routed to a programmable gain circuit which provides up to 9 dB of gain in 3 dB steps. The gain is adjustable through the Input Control Byte. Right and left channel gain settings are controlled independently with the GNR1/0 and GNL1/0 bits. Level changes occur immediately on register updates. To minimize audible artifacts, level changes should be done with the channel muted. The ADC Status Report Byte provides feedback of input level for each ADC channel. This register continously monitors the ADC output and records the peak output level since the last register read. Reading this register causes it to reset to 0 and peak monitoring begins again. a nominal 2.83 Vpp (1 Vrms) output with a 2.3 volt quiescent voltage for a full scale digital input. The recommended off-chip analog filter is a 2nd order Butterworth with a -3 dB corner at Fs, see Figure 3. This filter provides out-of-band noise attenuation along with a gain of 2, providing a 2 Vrms output signal. A 3rd order Butterworth filter with a -3dB corner at 0.75 Fs can be used if greater out of band noise filtering is desired. The CS4226 DAC interpolation filter is a linear phase design which has been pre-compensated for an external 2nd order Butterworth filter to provide a flat frequency response and linear phase response over the passband. If this filter is not used, small frequency response magnitude and phase errors will occur.
Output Level Attenuator
The DAC outputs are each routed through an attenuator which is adjustable in 1 dB steps. Output attenuation is available through the Output Attenuator Data Bytes. Level changes are implemented in the analog domain such that the noise is attenuated by the same amount as the signal , until the residual output noise is equal to the noise floor in the mute state; at this point attenation is implemented in the digital domain. The change from analog to digital attenuation occurs at -23 dB. Level changes only take effect on zero crossings to minimize audible artifacts. If there is no zero crossing, then the requested level change will occur after a time-out period between 512 and 1024 frames (11.6 ms to 23.2 ms at 44.1 kHz frame rate). There is a separate zero crossing detector for each channel. Each ACC bit (Acceptance bit) in the DAC Status Report Byte gives feedback on when a volume control change has taken effect. This bit goes high when a new setting is loaded and returns low when it has taken effect. Volume control changes can be instantaneous by setting the Zero Crossing Disable (ZCD) bit in the DAC Control Byte to 1. Each output can be independently muted via mute control bits, MUT6-1, in the DAC Control Byte.
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High Pass Filter
The operational amplifiers in the input circuitry driving the CS4226 may generate a small DC offset into the A/D converter. The CS4226 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The characteristics of this first-order high pass filter are outlined Table 2 below for an output sample rate of 44.1 kHz. This filter response scales linearly with sample rate.
Frequency Response Phase Deviation Passband Ripple -3dB @ 3.4 Hz -0.13 dB @ 20 Hz 10 degrees @ 20 Hz None
Table 2. High Pass Filter Characteristics
Analog Outputs Line Level Outputs
The CS4226 contains an on-chip buffer amplifier producing single-ended outputs capable of driving 10 k loads. Each output (AOUT 1-6) will produce
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CS4226
The mute also takes effect on a zero-crossing or after a timeout. In addition, the CS4226 has an optional mute on consecutive zeros feature, where all DAC outputs will mute if they receive between 512 and 1024 consecutive zeros (or -1 code) on all six channels. A single non-zero value will unmute the DAC outputs. This feature can be disabled with the MUTC bit in the DAC Control Byte. When using the internal PLL as the clock source, all DACs will instantly mute when the PLL detects an error. ternal crystal, by using the on-chip PLL, or by using an external clock source. In all modes it is required to have SCLK and LRCK synchronous to the selected master clock.
Clock Source
The CS4226 requires a high frequency master clock to run the internal logic. The Clock Source bits, CS0/1/2 in Clock Mode Byte, determine the source of the clock. A high frequency crystal can be connected to XTI and XTO, or a high frequency clock can be applied to XTI. In both these cases, the internal PLL is disabled, and the VCO turns off. The externally supplied high frequency clock can be 256 Fs, 384 Fs or 512 Fs; this is set by the CI0/1 bits in the Clock Mode Byte. When using the onchip crystal oscillator, external loading capacitors are required, see Figure 1. High frequency crystals (>8MHz) should be parallel resonant, fundamental mode and designed for 20 pF loading (equivalent to 40 pF to ground on each leg). Alternatively, the on-chip PLL may be used to generate the required high frequency clock. The PLL input clock is 1 Fs, and may be input from LRCKAUX, LRCK, or from XTI/XTO. In this last case, a 1 Fs clock may be input into XTI, or a 1 Fs crystal attached across XTI/XTO. When an external 1 Fs crystal is attached, extra components will be required, see Figure 1. The PLL will lock onto a new 1 Fs clock in about 90 ms. If the PLL input clock is removed, the VCO will drift to the low frequency end of its frequency range. The PLL can also be used to lock to an S/PDIF data source on RX1, RX2, RX3, or RX4. Source selection is accomplished with the CS2/1/0 bits in the Clock Mode Byte. The PLL will lock to an S/PDIF source in about 90 ms. Finally, the PLL has two filter loop current modes, normal and high current, that are selected via the LC bit in the Converter Control Byte. In the normal mode, the loop current is 25 A. In the high current
Clock Generation
The master clock to operate the CS4226 may be generated by using the on-chip inverter and an ex-
150pF 22 k 11 k AOUT 1000pF 5 k CMOUT 3.9 k _ + Example Op-Amps are MC33078 0.47 F
2-Pole Butterworth Filter
560 pF 5.85 k
1.1 k 4.75 k AOUT 5600 pF
1.21 k
_
5600 pF 5 k
+
CMOUT 0.47 F
3-Pole Butterworth Filter
Figure 3.
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CS4226
mode, the loop current is 300 A. The high current mode allows the use of lower impedance filter components which minimizes the influences of board contamination. See the table in Figure 1 for filter component values in each mode. of SCLK is chosen by setting the DSCK bit in the DSP Port Mode Byte. SCLK can be generated by the CS4226 (master mode) or it can be input from an external SCLK source (slave mode). Mode selection is set with the DMS1/0 bits in the DSP Port Mode Byte. The number of SCLK cycles in one system sample period is programmable to be 32, 48, 64, or 128 by setting the DCK1/0 bits in the DSP Port Mode Byte. The Left/Right clock (LRCK) is used to indicate left and right data and the start of a new sample period. It may be output from the CS4226, or it may be generated from an external controller. The frequency of LRCK must be equal to the system sample rate, Fs. SDIN1, SDIN2, and SDIN3 are the data input pins, each of which drive a pair of DACs. SDOUT1 and SDOUT2 can carry the output data from the two 20-bit ADC's, the mono ADC, the auxiliary digital audio port, and the S/PDIF receiver. Selection depends on the IS1/0 bits in the ADC control byte. The audio DSP port may also be configured so that all 6 DAC's data is input on SDIN1, and all 3 ADC's data is output on SDOUT1. Table 3 outlines the serial interface ports.
DAC Inputs SDIN1 left channel right channel single line SDIN2 left channel right channel SDIN3 left channel right channel
DAC #1 DAC #2 All 6 DAC channels DAC #3 DAC #4 DAC #5 DAC #6
Master Clock Output
CLKOUT is a master clock output provided to allow synchronization of external components. Available CLKOUT frequencies of 1 Fs, 256 Fs, 384 Fs, and 512 Fs, are selectable by the CO0/1 bits of the Clock Mode Byte. Generation of CLKOUT for 384 Fs and 512 Fs is accomplished with an on chip clock multiplier and may contain clock jitter. The source of the 256 Fs CLKOUT is the output of the PLL or a divided down clock from the XTI/XTO input. If 384 Fs is chosen as the input clock at XTI and 256 Fs is chosen as the output, CLKOUT will have approximately a 33% duty cycle. In all other cases CLKOUT will typically have a 50% duty cycle.
Synchronization
The DSP port and Auxiliary port must operate synchronously to the CS4226 clock source. The serial port will force a reset of the data paths in an attempt to resynchronize if non-synchronous data is input to the CS4226. It is advisable to mute the DACs when changing from one clock source to another to avoid the output of undesirable audio signals as the CS4226 resynchronizes.
Digital Interfaces
There are 3 digital audio interface ports: the audio DSP port, the auxiliary digital audio port, and the S/PDIF reciever. The serial data is represented in 2's complement format with the MSB-first in all formats.
Table 3. DSP Serial Interface Ports
Audio DSP Serial Interface Formats
The audio DSP port supports 7 alternate formats, shown in Figures 4, 5, and 6. These formats are chosen through the DSP Port Mode Byte with the DDF2/1/0 bits. Formats 5 and 6 are single line data modes where all DAC channels are combined onto a single input
13
Audio DSP Serial Interface Signals
The serial interface clock, SCLK, is used for transmitting and receiving audio data. The active edge
DS188F1
CS4226
FORMAT 0, 1, 2:
Format 0: M = 20 Format 1: M = 18 Format 2: M = 16
LRCK SCLK
SDIN LSB
Left
Right
MSB
LSB
MSB
LSB
M SCLKs
M SCLKs
Right
FORMAT 3:
LRCK SCLK
Left
SDIN
MSB
LSB
MSB
LSB
MSB
FORMAT 4:
LRCK SCLK SDIN MSB
Left
Right
LSB
MSB
LSB
Note: SCLK shown for DSCK = 0. SCLK inverted for DSCK = 1.
Figure 4. Audio DSP and Auxiliary Port Data Input Formats
FORMAT 0, 1, 2:
Format 0: M = 20 Format 1: M = 18 Format 2: M = 16
LRCK SCLK
SDOUT LSB
Left
Right
MSB
LSB
MSB
LSB
M SCLKs
M SCLKs
Right
FORMAT 3:
LRCK SCLK
Left
SDOUT
MSB
LSB
MSB
LSB
MSB
FORMAT 4:
LRCK SCLK SDOUT MSB
Left
Right
LSB
MSB
LSB
Note: SCLK shown for DSCK = 0. SCLK inverted for DSCK = 1.
Figure 5. Audio DSP Port Data Output Formats
64 SCLKS 64 SCLKS
FORMAT 5: LRCK
SCLK SDIN1 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB
DAC #1 20 clks SDOUT1 SDOUT1
DAC #3 20 clks SDOUT2
DAC #5 20 clks
DAC #2 20 clks SDOUT1
DAC #4 20 clks SDOUT2
DAC #6 20 clks
20 clks
20 clks
128 SCLKS
20 clks
20 clks
128 SCLKS
FORMAT 6: LRCK (out)
(MASTER MODE ONLY) SCLK (out)
SDIN1
MSB
LSB
MSB
LSB
MSB DAC #5 32 clks
LSB
MSB
LSB
MSB
LSB
MSB DAC #6 32 clks
LSB
DAC #1
32 clks SDOUT1 SDOUT1 32 clks
DAC #3
32 clks SDOUT2 32 clks
DAC #2
32 clks
DAC #4 32 clks SDOUT2 32 clks
SDOUT1
32 clks
Figure 6. One data line modes
14
DS188F1
CS4226
and all ADC channels are combined onto a single output. Format 6 is available in Master Mode only. See figure 6 for details. RX1, RX2, RX3, or RX4 can be chosen as the S/PDIF input source. The PLL will lock to the requested data source and setting IS1/0 = 1 or 2 in the ADC Control Byte routes the recovered output to SDOUT1 (channel A to left, channel B to right). All 24 received data bits will pass through the part to SDOUT1 except when the serial port is configured with 32 SCLK's per frame or in Format 5. For these cases, the 16 or 20 MSB's respectively will be output. The error flags are reported in the Receiver Status Byte. The LOCK bit indicates whether the PLL is locked to the incoming S/PDIF data. Parity, Biphase, or Validity errors (PAR=1, BIP=1 or V=1) will cause the last valid data sample to be held at the receiver input until the error condition no longer is present (see Hold section). Mute on extended hold can also be enabled through the Auxiliary Port Control Byte (see Hold section). Other error flags include confidence, CONF, and cyclic redundancy check, CRC. The CONF flag occurs when the received data eye opening is less than half a bit period. This indicates that the quality of the transmission link is poor and does not meet the digital audio interface standards. The CRC flag is updated at the beginning of a channel status block and is only valid when the professional format of channel status data is received. This error indicates when the CS4226 calculated CRC value does not match the CRC byte of the received channel status block. The OVL/ERR pin will go high to flag an error. It is a latched logical OR of the Parity, Biphase, Validity, and Lock error flags in the Receiver Status Byte which is reset at the end of each frame. However, Parity, Biphase, or Validity errors can be masked from the pin by clearing the PM, BM, and VM bits respectively, of the Input Control Byte. The first four bytes of the Channel Status block for both channel A and B can be accessed in the Receiver Channel Status Bytes. When the CV bit is
15
Auxiliary Audio Port Signals
The auxiliary port provides an alternate way to input digital audio signals into the CS4226, and allows the CS4226 to synchronize the system to an external digital audio source. This port consists of serial clock, data and left/right clock pins named, SCLKAUX, DATAUX and LRCKAUX. The Auxiliary Audio Port input is output on SDOUT1 when the IS bits are set to 1 or 2 in the ADC Control Byte. Additionally, setting IS to 2 routes the stereo ADC outputs to SDOUT2. There is approximately a two frame delay from DATAUX to SDOUT1. When the auxiliary port is used, the frequency of LRCKAUX must equal to the system sample rate, Fs, but no particular phase relationship is required. De-emphasis and muting on error conditions can be performed on input data to the auxiliary audio port; this is controlled by the Auxiliary Port Control Byte.
Auxiliary Audio Port Formats
Data input on DATAUX is clocked into the part by SCLKAUX using the format selected in the Auxiliary Port Mode Byte. The auxiliary audio port supports the same 5 formats as the audio DSP port in multi-data line mode. LRCKAUX is used to indicate left and right data samples, and the start of a new sample period. SCLKAUX and LRCKAUX may be output from the CS4226, or they may be generated from an external source, as set by the AMS1/0 control bits in the Auxiliary Port Mode Byte.
S/PDIF Receiver
The CS4226 reconfigures its auxiliary digital audio port as an S/PDIF receiver if CS2/1/0 in the Clock Mode Byte are set to be 4, 5, 6, or 7. In this mode
DS188F1
CS4226
high, these bytes are being updated and may be invalid. Additionally, the audio/non-audio, AC3/MPEG data stream indicator and sampling frequency channel status bits may be output to pins 9, 10, 11 and 12, respectively, see Table 4. This is accomplished by setting the CSP bit to 1 in the Auxiliary Status Output Byte. The FREQ0/1 channel status bit outputs are decoded from the sampling frequency channel status bits after first referencing channel status byte 0, bit 0 (PRO or consumer bit) which indicates the appropriate location of these bits in the channel status data stream. The received user bit is output on the HOLD/RUBIT pin if the HPC bit in the AUX Port Control Byte is set to 1. It can be sampled with the rising or falling edge of LRCK if the audio DSP port is in Master Mode.
AUDIO Pin 9 0 - Audio data 1 - Non-audio data 0 - No preamble detected in last 4096 frames 1 - Preamble detected 00 - 44.1 kHz 01 - 48 kHz 10 - Reserved 11 - 32 kHz
is detected, the AUTODATA indicator (pin 10) will go high. If no additional sync codes are detected within the next 4096 frames, the AUTODATA indicator pin will return low until another sync code is detected.
Control Port Signals
The control port is used to load all the internal settings. The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and I2C, with the CS4226 as a slave device. The SPI mode is selected by setting the I2C/SPI pin low, and I2C is selected by setting the I2C/SPI pin high. The state of this pin is continuously monitored.
SPI Mode
In SPI mode, CS is the CS4226 chip select signal, CCLK is the control port bit clock, (input into the CS4226 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller, and the chip address is 0010000. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 7 shows the control port timing in SPI mode. To write to a register, bring CS low. The first 7 bits on CDIN form the chip address, and they must be 0010000. The eighth bit is a read/write indicator (R/W), which should be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next 8 bits are the data which will be placed into register designated by the MAP. During writes, the CDOUT output stays in the high impedance state. It may be externally pulled high or low with a 47 k resistor. The CS4226 has a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, then the MAP will stay constant for
DS188F1
AUTODATA Pin 10
FREQ0/1
Pin 11/12
Table 4. S/PDIF Receiver Status Outputs
AC-3/MPEG Auto Detection
For AC-3/MPEG applications, it is important to know whether the incoming S/PDIF data stream is digital audio or compressed AC-3/MPEG data. This information is typically conveyed by setting channel status bit 1 (audio/non-audio bit), but some AC-3/MPEG sources may not strictly adhere to this convention and the bit may not be properly set. The CS4226 S/PDIF receiver has the capability to automatically detect whether the incoming data is a compressed AC-3/MPEG input. This is accomplished by looking for an AC-3/MPEG 96-bit sync code consisting of six 16-bit words. The 96-bit sync code consists of: 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the sync code
16
CS4226
successive reads or writes. If INCR is set to a 1, then MAP will auto increment after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. The auto MAP increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecutively. the 7 bit address field must be 00100. To communicate with a CS4226, the LSBs of the chip address field, which is the first byte sent to the CS4226, should match the settings of the AD1, AD0 pins. The eighth bit of the address bit is the R/W bit (high for a read, low for a write). The next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a write, the next byte is the data to be written to the register pointed to by the MAP. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP, allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. I2C bus is a registered trademark of Philips Semiconductors.
I2C Mode
In I2C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL, with the clock to data relationship as shown in Figure 8. There is no CS pin. Pins AD0, AD1 form the partial chip address. The upper 5 bits of
CS CCLK CHIP ADDRESS CDIN
0010000
R/W
Control Port Bit Definitions
All registers can be written and read back, except the DAC Status Report Byte, ADC Status Report Byte, Receiver Status Byte, and the Receiver Channel Status Bytes, which are read only. See the bit definition tables for bit assignment information.
MAP
MSB
DATA
LSB
CHIP ADDRESS
0010000
R/W
byte 1
byte n
MSB LSB MSB LSB
CDOUT
MAP = Memory Address Pointer
High Impedance
Figure 7. Control Port Timing, SPI mode
Note 1
SDA
00100 ADDR AD1-0
R/W
ACK
DATA 1-8
DATA ACK 1-8
ACK
SCL Start Stop
Note 1: If operation is a write, this byte contains the Memory Address Pointer, MAP. 2
Figure 8. Control Port Timing, I C Mode
DS188F1
17
CS4226
Power-up/Reset/Power Down Mode
Upon power up, the user should hold PDN=0 until the system's power supply has stabilized. In this state, the control port is reset to its default settings. When PDN goes high, the device remains in a low power mode in which the control port is active, but CMOUT will not supply current. The desired settings should be loaded in while keeping the RS bit set to 1. Normal operation is achieved by setting the RS bit to zero in the Converter Control Byte. Once set to 0, the part powers up and an offset calibration occurs. This process lasts approximately 50 ms. Reset/power down is achieved by lowering the PDN pin causing the part to enter power down. Once PDN goes high, the control port is functional and the desired settings should be loaded in while keeping the RS bit set to 1. The remainder of the chip remains in a low power reset state until the RS bit in the Converter Control Byte is set to 0. The CS4226 will also enter a stand-by mode if the master clock source stops for approximately 10 s or if the LRCK is not synchronous to the master clock. The control port will retain its current settings when in stand-by mode. Additional calibrations can be implemented by setting CAL to 0 and then to 1.
De-Emphasis
The S/PDIF receiver can be enabled to process 24 bits of received data (20 bits of audio data and four auxiliary bits) or process 20 bits of audio data (no auxiliary bits). Setting DEM24=0 in the Auxiliary Port Control Byte, will enable all 24 received data bits to be processed with de-emphasis when de-emphasis is enabled. When setting DEM24=1, the four auxiliary bits in the receiver data stream will pass through unchanged and only the 20 audio data bits will be processed. The CS4226 is capable of digital de-emphasis for 32, 44.1, or 48 kHz sample rates. Implementation of digital de-emphasis requires reconfiguration of the digital filter to maintain the filter response shown in Figure 9 at multiple sample rates. The Auxiliary Port Control Byte selects the de-emphasis control method. De-emphasis may be enabled under hardware control, using the DEM pin (DEM2/1/0=4,5,6), by software control using the DEM bit (DEM2/1/0=0,1,2,3), or by the emphasis bits in the channel status data when the S/PDIF receiver is chosen as the clock source (DEM2/0/1=7). If no frequency information is present, the filter defaults to 44.1 kHz.
Gain dB T1=50 s 0dB
DAC Calibration
Output offset voltage is minimized by an internal calibration cycle. A calibration will automatically occur anytime the part comes out of reset, including the power-up reset, when the master clock source to the part changes by changing the CS or CI bits in the Clock Mode Byte or when the PLL goes out of lock and then re-locks. The CS4226 can be re-calibrated whenever desired. A control bit, CAL, in the Converter Control Byte, is provided to initiate a calibration. The sequence is: 1) Set CAL to 1, the CS4226 sets CALP to 1 and begins to calibrate. 2) CALP will go to 0 when the calibration is completed.
18
T2 = 15 s -10dB
F1
F2
Frequency
Figure 9. De-emphasis Curve
DS188F1
CS4226
HOLD Function
If the digital audio source presents invalid data to the CS4226, the CS4226 may be configured to cause the last valid digital input sample to be held constant. Holding the previous output sample occurs when the user asserts the HOLD pin (HOLD=1) at any time during the stereo sample period, or if a parity, biphase, or validity error occurs when receiving S/PDIF data. Parity, biphase, and validity errors can be independently masked so that no hold occurs. This is done using the VM, PM, and BM bits in the Input Control Byte. During a HOLD condition, AUXPort (S/PDIF) input data is ignored. DAC outputs can be automatically muted after an extended HOLD period (>15 samples) by setting the MOH (Mute On Hold) bit = 0 in the Auxiliary Port Control Byte. DACs will not be automatically muted when MOH=1. When the S/PDIF error condition is removed or the HOLD pin is de-asserted (HOLD=0), the DAC outputs will return to one of two different states controlled by the UMV (Unmute on Valid Data) bit in the Auxiliary Port Control Byte. When UMV=0, the DAC outputs will unmute when the error is removed. When UMV=1, the DACs must be unmuted in the DAC Control Byte after the error is removed. This allows the user to unmute the DAC after the invalid data has passed through the DSP. DGND should be connected together at the CS4226. DGND for the CS4226 should not be confused with the ground for the digital section of the system. The CS4226 should be positioned over the analog ground plane near the digital/analog ground plane split. The analog and digital ground planes must be connected elsewhere in the system. The CS4226 evaluation board, CDB4226, demonstrates this layout technique. This technique minimizes digital noise and insures proper power supply matching and sequencing. Decoupling capacitors for VA, VD, and CMOUT should be located as close to the device package as possible. See Crystal's Application Note AN018: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, and the CDB4226 evaluation board data sheet for recommended layout of the decoupling components. The CS4226 will mute the analog outputs and enter the Power Down Mode if the supply drops below approximately 4 volts.
ADC and DAC Filter Response Plots
Figures 10 through 15 show the overall frequency response, passband ripple and transition band for the CS4226 ADC's and DAC's.
Power Supply, Layout, and Grounding
As with any high resolution converter, the CS4226 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 1 shows the recommended power arrangement with VA connected to a clean +5V supply. VD should be derived from VA through a 2 ohm resistor. VD should not be used to power additional circuitry. Pins 18, 20, 39 and 41, AGND and
DS188F1
19
CS4226
0 -10 -20 -30 -40 -50 dB -60 -70 -80 -90 -100 -110 -120 -130 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Normalized Frequency (Fs) dB
0.02
0.01
0.00
-0.01
-0.02 0.0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency (Fs)
Figure 10. 20-bit ADC Filter Response
0 -10 -20 -30 -40 -50 dB -60 -70 -80 -90 -100 -110 -120 0.40 0.45 0.50 0.55 0.6 0.65 0.70
Figure 11. 20-bit ADC Passband Ripple
0 -10 -20 -30 -40 -50 -60 dB -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized Frequency (Fs)
Normalized Frequency (Fs)
Figure 12. 20-bit ADC Transition Band
0
Figure 13. DAC Frequency Response
0.02
-10 -20 -30
0.01
-40 -50 dB
dB
-60 -70 -80 -90
0.00
-0.01
-100 -110 -120
-0.02 0.0 0.1 0.2 0.3 0.4 0.5 Normalized Frequency (Fs)
0.40
0.45
0.50
0.55
0.6
0.65
0.70
Normalized Frequency (Fs)
Figure 14. DAC Passband Ripple
Figure 15. DAC Transition Band
20
DS188F1
CS4226
REGISTER DESCRIPTION
Memory Address Pointer (MAP)
B7 INCR B6 0 B5 0 B4 MAP4 B3 MAP3 B2 MAP2 B1 MAP1 B0 MAP0
MAP4-MAP0 INCR
Register Pointer Auto Increment Control Bit 0 - No auto increment 1 - Auto increment on
This register defaults to 01h.
Reserved Byte (0)
This byte is reserved for internal use and must be set to 00h for normal operation. This register defaults to 00h.
Clock Mode Byte (01h)
B7 0 B6 CO1 B5 CO0 B4 CI1 B3 CI0 B2 CS2 B1 CS1 B0 CS0
CS2-CS0
Sets the source of the master clock. 0 - Crystal Oscillator or XTI at high frequency (PLL disabled) 1 - PLL driven by LRCKAUX at 1 Fs 2 - PLL driven by LRCK at 1 Fs 3 - PLL driven by XTI at 1 Fs 4 - PLL driven by RX1 data. This changes AUX port to S/PDIF port. 5 - PLL driven by RX2 data. This changes AUX port to S/PDIF port. 6 - PLL driven by RX3 data. This changes AUX port to S/PDIF port. 7 - PLL driven by RX4 data. This changes AUX port to S/PDIF port. Determines frequency of XTI when PLL is disabled (not used if CS 0) 0 - 256 Fs 1 - 384 Fs 2 - 512 Fs 3 - not used Sets CLKOUT frequency 0 - 256 Fs 1 - 384 Fs 2 - 512 Fs 3 - 1 Fs
CI1-CI0
CO1-CO0
This register defaults to 01h. NOTE: If the sample rate on an input pin changes while using the PLL with RX1, RX2, RX3 or RX4, the PLL will not resynchronize to the new sample rate. You must either change input pins or change the Clock Mode Byte to something else and then change it back to the correct value. This will cause the PLL to resync.
DS188F1
21
CS4226
Converter Control Byte (02h)
B7 CALP B6 CLKE B5 DU B4 AUTO B3 LC B2 0 B1 CAL B0 RS
RS
Chip reset (Do not clear this bit until all registers have been configured as desired) 0 - No Reset 1 - Reset Calibration control bit 0 - Normal operation 1 - Rising edge initiates calibration Loop Current 0 - Normal Mode, 25A PLL loop current (See Figure 1 for filter component values) 1 - High Current Mode, 300 A PLL loop current (See Figure 1 for filter component values)
CAL
LC
The following bits are read only: AUTO AC3 and MPEG Automatic Detection 0 - No AC3/MPEG Detected 1 - AC3/MPEG detected on RX/AUX Shows selected De-Emphasis setting used by DAC's 0 - Normal Flat DAC frequency response 1 - De-Emphasis selected Clocking system status 0 - No errors 1 - PLL is not locked, crystal is not oscillating, or requesting clock change in progress Calibration status 1 - Calibration in progress 0 - Calibration doneThis register defaults to 01h
DU
CLKE
CALP
This register defaults to 01h NOTE: The AC3 and MPEG detection for the AUTO bit does not look at the channel status bits. This bit is determined by looking for the AC3/MPEG header in the data stream. See the "AC3/MPEG Auto Detection" section earlier in the datasheet for more details.
DAC Control Byte (03h)
B7 ZCD B6 MUTC B5 MUT6 B4 MUT5 B3 MUT4 B2 MUT3 B1 MUT2 B0 MUT1
MUT6-MUT1
Mute control bits 0 - Normal output level 1 - Selected DAC output muted Controls mute on consecutive zeros function 0 - 512 consecutive zeros will mute DAC 1 - DAC output will not mute on zeros Zero crossing disable 0 - DAC mutes and volume control changes occur on zero-crossings. 1 - DAC mutes and volume control changes occur immediately.
MUTC
ZCD
This register defaults to 3Fh.
22
DS188F1
CS4226
Output Attenuator Data Byte (04h, 05h, 06h, 07h, 08h, 09h)
B7 0 B6 ATT6 B5 ATT5 B4 ATT4 B3 ATT3 B2 ATT2 B1 ATT1 B0 ATT0
ATT6-ATT0
Sets attenuator level 0 - No attenuation 127 - 127 dB attenuation ATT0 represents 1.0 dB of attenuation
This register defaults to 7Fh.
DAC Status Report Byte (Read Only) (0Ah)
B7 0 B6 B5 ACC6 B4 ACC5 B3 ACC4 B2 ACC3 B1 ACC2 B0 ACC1
ACC6-ACC1
Acceptance Bit 1 - New setting is waiting for zero-crossing to be accepted. 0 - ATT6-ATT0 has been accepted.
This register is read-only.
ADC Control Byte (0Bh)
B7 IS1 B6 IS0 B5 0 B4 AIS1 B3 AIS0 B2 MUTM B1 MUTR B0 MUTL
MUTL, MUTR, MUTM - Left, right and mono channel mute control 0 - Normal output level 1 - Selected ADC output muted AIS1-AIS0 ADC analog input mux control 0 - Selects stereo pair 1 1 - Selects stereo pair 2 2 - Selects stereo pair 3 3 - Differential Input Input mux selection 0 - Stereo ADC output to SDOUT1, Mono ADC output to SDOUT2 1 - Auxiliary Digital Input Port or S/PDIF Reciever to SDOUT1, Mono ADC output to SDOUT2 2 - Auxiliary Digital Input Port or S/PDIF Receiver to SDOUT1, Stereo ADC output to SDOUT2 3 - Not used.
IS1-IS0
This register defaults to 00h.
DS188F1
23
CS4226
Input Control Byte (0Ch)
B7 OVRM B6 VM B5 BM B4 PM B3 GNR1 B2 GNR0 B1 GNL1 B0 GNL0
OVRM
ADC Overflow Mask 0- Error condition is masked at OLV/ERR pin and no DAC muting on extended hold 1- No Masking Validity Error Mask 0- Error condition is masked at OLV/ERR pin and no DAC muting on extended hold 1- No Masking Biphase Error Mask 0- Error condition is masked at OLV/ERR pin and no DAC muting on extended hold 1- No Masking Parity Error Mask 0- Error condition is masked at OLV/ERR pin and no DAC muting on extended hold 1- No Masking Sets left input gain 0 - 0 dB 1 - 3 dB 2 - 6 dB 3 - 9 dB Sets right input gain 0 - 0 dB 1 - 3 dB 2 - 6 dB 3 - 9 dB
VM
BM
PM
GNL1-GNL0
GNR1-GNR0
This register defaults to 00h.
ADC Status Report Byte (Read Only) (0Dh)
B7 LVM1 B6 LVM0 B5 LVR2 B4 LVR1 B3 LVR0 B2 LVL2 B1 LVL2 B0 LVL0
LVL2-LVL0, LVR2-0 Left and Right ADC output level 0 - Normal output levels 1 - -6 dB level 2 - -5 dB level 3 - -4 dB level 4 - -3 dB level 5 - -2 dB level 6 - -1 dB level 7 - Clipping LVLM1-LVLM0 Mono ADC output level 0 - Normal output level 1 - -6 dB level 2 - -3 dB level 3 - Clipping
These bits are 'sticky'. They constantly monitor the ADC output for the peak levels and hold the maximum output. They are reset to 0 when read. This register is read only.
24
DS188F1
CS4226
DSP Port Mode Byte (0Eh)
B7 DCK1 B6 DCK0 B5 DMS1 B4 DMS0 B3 DSCK B2 DDF2 B1 DDF1 B0 DDF0
DDF2-DDF0
Data format 0 - Right justified, 20-bit 1 - Right justified, 18-bit 2 - Right justified, 16-bit 3 - Left justified, 20-bit in / 24-bit out 4 - I2S compatible, 20-bit in / 24-bit out 5 - One Data Line Mode (Fig. 6) 6 - One Data Line (Master Mode only, Fig. 6) 7 - Not used Set the polarity of clocking data 0 - Data clocked in on rising edge of SCLK, out on falling edge of SCLK 1 - Data clocked in on falling edge of SCLK, out on rising edge of SCLK Sets the mode of the port 0 - Slave 1 - Master Burst - SCLKs are gated 128 fs clocks 2 - Master Non-Burst - SCLKs are evenly distributed (No 48 fs SCLK) 3 - not used - default to Slave Set number of bit clocks per Fs period 0 - 128 1 - 48 - Master Burst or Slave mode only 2 - 32 - All formats will default to 16 bits 3 - 64
DSCK
DMS1-DMS0
DCK1-DCK0 *
This register defaults to 00h. * DCK1-DCK0 are ignored in formats 5 and 6.
DS188F1
25
CS4226
Auxiliary Port Mode Byte (0Fh)
B7 ACK1 B6 ACK0 B5 AMS1 B4 AMS0 B3 ASCK B2 ADF2 B1 ADF1 B0 ADF0
This byte is not available when the receiver is functioning. ADF2-ADF0 Data format 0 - Right justified, 20-bit data 1 - Right justified, 18-bit data 2 - Right justified, 16-bit data 3 - Left justified, 20-bit 4 - I2S compatible, 20-bit 5 - Not used 6 - Not used 7 - Not used Sets the polarity of clocking data 0 - Data clocked in on rising edge of SCLKAUX 1 - Data clocked in on falling edge of SCLKAUX Sets the mode of the port. 0 - Slave 1 - Master Burst - SCLKAUXs are gated 128 fs clocks 2 - Master Non-Burst - SCLKAUXs are evenly distributed in LRCKAUX frame 3 - Not used - default to slave Set number of bit clocks per Fs period. 0 - 128 1 - 48 - Master Burst or Slave mode only 2 - 32 - All input formats will default to 16 bits. 3 - 64
ASCK
AMS1-AMS0
ACK1-ACK0
This register defaults to 00h.
26
DS188F1
CS4226
Auxilliary Port Control Byte (10h)
B7 CSP B6 HPC B5 UMV B4 MOH B3 DEM24 B2 DEM2 B1 DEM1 B0 DEM0
DEM 2-0
Selects de-emphasis response/source 0 - De-emphasis off 1 - De-emphasis on 32 kHz 2 - De-emphasis on 44.1 kHz 3 - De-emphasis on 48 kHz 4 - De-emphasis pin 32 kHz 5 - De-emphasis pin 44.1 kHz 6 - De-emphasis pin 48 kHz 7 - S/PDIF receiver channel status bits Process AUX data LSBs 0 - All received data bits (24 max) are processed 1 - Top 20 bits processed with De-emphasis filter. 4 AUX LSBs are passed unchanged. Mute On Hold 0 - Extended Hold (16 frames) mutes DAC outputs 1 - DACs not muted Unmute on Valid Data 0 - DACs unmute when ERROR is removed 1 - DACs must be unmuted in DAC control byte after ERROR is removed. HOLD/RUBIT Pin Control 0 - HOLD/RUBIT is an input (HOLD) 1 - HOLD/RUBIT is an output(RUBIT) Channel Status output to pins. 0 - Analog inputs to pins. AIN2R, AIN2L, AIN3R, AIN3L 1 - Channel status to pins. (This forces AIS1/0=0)
DEM24
MOH
UMV
HPC
CSP
This register defaults to 00h.
DS188F1
27
CS4226
Receiver Status Byte (Read Only) (11h)
B7 CV B6 0 B5 CRC B4 LOCK B3 V B2 CONF B1 BIP B0 PAR
PAR
Parity bit 0 - No error 1 - Error Biphase bit 0 - No error 1 - Error Confidence bit 0 - No error 1 - Error Validity bit 0 - No error 1 - Error PLL lock bit 0 - PLL locked 1 - Out of lock Cyclic Redundacy check bit 0 - No error 1 - Error on either channel Channel status validity 0 - Valid 1 - Not valid, data is updating
BIP
CONF
V
LOCK
CRC
CV
This register is read only.
Receiver Channel Status Byte (Read Only) (12h, 13h, 14h, 15h, 16h, 17h, 18h, 19h)
B7 CS7 B6 CS6 B5 CS5 B4 CS4 B3 CS3 B2 CS2 B1 CS1 B0 CS0
Byte 12h Byte 13h Byte 14h Byte 15h Byte 16h Byte 17h Byte 18h Byte 19h
Channel A Channel A Channel A Channel A Channel B Channel B Channel B Channel B
Status Byte 1 Status Byte 2 Status Byte 3 Status Byte 4 Status Byte 1 Status Byte 2 Status Byte 3 Status Byte 4
Bit definition changes depending upon PRO bit setting. When CV = 1, these bits are updating and may be invalid.
28
DS188F1
CS4226
PIN DESCRIPTION
DGND2 VD+ DGND1 RX1 SCLKAUX/RX2 LRCKAUX/RX3 DATAUX/RX4 HOLD/RUBIT SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS 2 I C/SPI PDN AIN3R/AUDIO AIN3L/AUTODATA AIN2L/FREQ0 AIN2R/FREQ1 AIN1R AIN1L AINAUX CMOUT SCLK LRCK SDOUT1 SDOUT2 SDIN1 SDIN2 SDIN3 CLKOUT OVL/ERR XTO XTI DEM AOUT6 AOUT5 AOUT4 AOUT3 AOUT2 AOUT1 AGND2 VA+ AGND1 FILT
44 42 40 38 36 34 33 1 2 32 31 3 30 4 5 29 top 28 6 view 7 27 26 8 9 25 24 10 11 23 12 14 16 18 20 22
Power Supply
VA+ - Analog Power Input, PIN 19. +5 V analog supply. AGND1, AGND2 - Analog Ground, PINS 18, 20. Analog grounds. VD+ - Digital Power Input, PIN 40. + 5 V digital supply. DGND1, DGND2 - Digital Ground, PINS 41, 39. Digital grounds.
DS188F1
29
CS4226
Analog Inputs
AIN1L, AIN1R - Left and Right Channel Mux Input 1, PINS 14, 13. Analog signal input connections for the right and left channels for multiplexer input 1. AIN2L/FREQ0, AIN2R/FREQ1 - Left & Right Channel Mux Input 2/Channel Status Freq. Bits, PINS 11, 12. Analog signal input connections for the right and left channels for multiplexer input 2. When CSP = 1, these pins are configured as channel status outputs indicating the sampling frequency. AIN3L/AUTODATA, AIN3R/AUDIO - Left & Right Channel Mux Input 3/AC3 and MPEG Detect Output, PINS 10, 9. Analog signal input connections for the right and left channels for multiplexer input 3. When CSP = 1, AIN3L is configured as an output indicating the presence of an AC-3 or MPEG data stream at the RX input and AIN3R is configured as a channel status output indicating audio/non-audio data at the RX input. AINAUX - Auxiliary Line Level Input, PIN 15. Analog signal input for the mono A/D converter. Analog Outputs AOUT1, AOUT2, AOUT3, AOUT4, AOUT5, AOUT6 - Audio Outputs, PINS 21 - 26. The analog outputs from the 6 D/A converters. Each output can be independently controlled for output amplitude. CMOUT - Common Mode Output, PIN 16. This common mode voltage output may be used for level shifting when DC coupling is desired. The load on CMOUT must be DC only, with an impedance of not less than 50 k. CMOUT should be bypassed with a 1.0 F to AGND. Digital Audio Interface Signals SDIN1 - Serial Data Input 1, PIN 34. Digital audio data for the DACs 1 and 2 is presented to the CS4226 on this pin. This pin is also used for one-line data input modes. SDIN2 - Serial Data Input 2, PIN 33. Digital audio data for the DACs 3 and 4 is presented to the CS4226 on this pin. SDIN3 - Serial Data Input 3, PIN 32. Digital audio data for the DACs 5 and 6 is presented to the CS4226 on this pin.
30
DS188F1
CS4226
SDOUT1- Serial Data Output 1, PIN36. Digital audio data from the 20-bit stereo audio ADCs is output from this pin. When IS = 1 or 2, DATAAUX or the S/PDIF receiver is output on SDOUT1. This pin is also used for one line data output modes. SDOUT2 - Serial Data Output 2, PIN 35. Digital audio data from the mono audio ADC is output from this pin. When IS = 2, the stereo audio ADC's are output from this pin SCLK - Serial Port Clock I/O, PIN 38. SCLK clocks digital audio data into the DACs via SDIN1/2/3, and clocks data out of the ADCs on SDOUT1/2. Active clock edge depends on the DSCK bit. LRCK - Left/Right Select Signal I/O, PIN 37. The Left/Right select signal. This signal has a frequency equal to the sample rate. The relationship of LRCK to the left and right channel data depends on the selected format. DEM - De-emphasis Control, PIN 27. When low, DEM controls the activation of the standard 50/15 s de-emphasis filter for either 32, 44.1, or 48 kHz sample rates. This pin is enabled by the DEM2-0 bits in the Auxiliary Port Control Byte. OVL/ERR - Overload Indicator, PIN 30. This pin goes high if either of the stereo audio ADCs or the mono ADC is clipping. If the S/PDIF receiver is chosen as the clock source (CS = 4, 5, 6, 7), then the pin also goes high if there is an error in the Receiver Status Byte. Error and overloading can be masked using bits in the Input Control Byte. Auxillary Digital Audio and S/PDIF Receiver Signals RX1 - Receiver Channel 1, PIN 42. This pin is a dedicated S/PDIF input channel configured as the clock source for the device via the CS2-0 bits. DATAUX/RX4 - Auxiliary Data Input / Receiver Channel 4, PIN 1. DATAUX is the auxiliary audio data input line, usually connected to an external digital audio source. As RX4, this pin is configured as S/PDIF input channel 4 via the control port. LRCKAUX/RX3 - Auxiliary Word Clock Input or Output / Receiver Channel 3, PIN 44. In auxiliary slave mode, LRCKAUX is a word clock (at Fs) from an external digital audio source. LRCKAUX can be used as the clock reference for the internal PLL. In auxiliary master mode, LRCKAUX is a word clock output (at Fs) to clock an external digital audio source. As RX3, this pin is configured as S/PDIF input channel 3 via the control port.
DS188F1
31
CS4226
SCLKAUX/RX2 - Auxiliary Bit Clock Input or Output / Receiver Channel 2, PIN 43. In auxiliary slave mode, SCLKAUX is the serial data bit clock from an external digital audio source, used to clock in data on DATAAUX. In auxiliary master mode, SCLKAUX is a serial data bit clock output. As RX2, this pin is configured as S/PDIF input channel 2 via the control port. HOLD/RUBIT - S/PDIF Received User Bit / HOLD Control, PIN 2. When the S/PDIF receiver is chosen as the clock source (CS = 4, 5, 6 and HPC = 1), then this pin outputs the received user bit. When HPC = 0, this pin is sampled on the active edge of SCLKAUX. If it is high any time during the frame, DATAUX data is ignored and the previous "good" sample is output to the serial output port. Control Port Signals I2C/SPI - Control Port Format, PIN 7. Setting this pin high configures the control port for the I2C interface; a low state configures the control port for the SPI interface . The state of this pin sets the function of the control port input/output pins . SCL/CCLK - Serial Control Interface Clock, PIN 3. SCL/CCLK is the serial control interface clock, and is used to clock control bits into and out of the CS4226. AD0/CS - Address Bit / Control Port Chip Select, PIN 6. In I2C mode, AD0 is a chip address bit. In SPI software control mode, CS is used to enable the control port interface on the CS4226. AD1/CDIN - Address Bit / Serial Control Data In, PIN 5. In I2C mode, AD1 is a chip address bit. In SPI software control mode, CDIN is the input data line for the control port interface. SDA/CDOUT - Serial Control Data Out, PIN 4. In I2C mode, SDA is the control data I/O line. In SPI software control mode, CDOUT is the output data from the control port interface on the CS4226. Clock and Crystal Pins XTI, XTO - Crystal connections, PIN 28, 29. Input and output connections for the crystal which may be used to operate the CS4226. Alternatively, a clock may be input into XTI. CLKOUT - Master Clock Output, PIN 31. CLKOUT allows external circuits to be synchronized to the CS4226. Alternate output frequencies are selectable by the control port.
32 DS188F1
CS4226
Miscellaneous Pins
FILT - PLL Loop Filter Pin, PIN 15. A capacitor, CFILT, in series with a resistor, RFILT, should be connected from FILT to AGND. Additionally a capacitor, CRIP, should be placed in parallel with CFILT and RFILT. See Figure 1 for recommended component values. PDN - Powerdown Pin, PIN 8. When low, the CS4226 enters a low power mode and all internal states are reset, including the control port. When high, the control port becomes operational and the RS bit must be cleared before normal operation will occur.
DS188F1
33
CS4226
PARAMETER DEFINITIONS
Dynamic Range The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbFs signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 20 Hz to 20 kHz), including distortion components. Expressed in decibels. ADCs are measured at -1dBFs as suggested in AES 17-1991 Annex A. Idle Channel Noise / Signal-to-Noise-Ratio The ratio of the rms analog output level with 1 kHz full scale digital input to the rms analog output level with all zeros into the digital input. Measured A-weighted over a 10 Hz to 20 kHz bandwidth. Units in decibels. This specification has been standardized by the Audio Engineering Society, AES17-1991, and referred to as Idle Channel Noise. This specification has also been standardized by the Electronic Industries Association of Japan, EIAJ CP-307, and referred to as Signal-to-Noise-Ratio. Total Harmonic Distortion (THD) THD is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. Units in decibels. Interchannel Isolation A measure of crosstalk between channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Frequency Response A measure of the amplitude response variation from 20Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units are in decibels. Gain Error The deviation from the nominal full scale output for a full scale input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input grounded. For the DACs, the deviation of the output from zero (relative to CMOUT) with midscale input code. Units are in volts.
34 DS188F1
CS4226
PACKAGE DIMENSIONS
44L TQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES DIM A A1 B D D1 E E1 e L MIN 0.000 0.002 0.012 0.478 0.404 0.478 0.404 0.029 0.018 0.000 MAX 0.065 0.006 0.018 0.502 0.412 0.502 0.412 0.037 0.030 7.000 MILLIMETERS MIN MAX 0.00 1.60 0.05 0.15 0.30 0.45 11.70 12.30 9.90 10.10 11.70 12.30 9.90 10.10 0.70 0.90 0.45 0.75 0.00 7.00
JEDEC # : MS-026
DS188F1
35
* Notes *
CDB4226
Evaluation Board for CS4226
Features General Description
The CDB4226 is useful for evaluating the performance of the CS4226. Up to three stereo input sources can be connected to the evaluation board, one of which is selected for A/D conversion. Six channels of D/A conversion allow for multi-channel applications such as Dolby Pro-Logic, Dolby Digital (AC-3), THX, and DSPbased soundfield applications. S/PDIF I/O support is provided by the CS4226's on-chip S/PDIF receiver and a CS8402A S/PDIF transmitter. For serial audio connections, access to the part's auxiliary and DSP ports is also provided. The board can be configured and controlled by a peripheral serial control port. The peripheral control options are SPI and I2C. PC software which supports the board's SPI interface is provided, and can be used to set the internal control registers of the CS4226. ORDERING INFORMATION CDB4226 Evaluation Board
l CS4226 - Six 20-bit D/A Converters, Stereo
20-bit A/D Converters, Mono 20 bit A/D Converter, S/PDIF Receiver l Multiple Stereo Input Source Selection l Input and Output of Serial Audio Data Through Auxiliary and DSP Ports l Input and Output of S/PDIF Interface Signals Through Coaxial and Optical Connections l Control of CS4226 via SPI Software Interface l Multiple Clock Options Available
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved)
FEB `97 DS188DB1 37
CDB4226
CDB4226 SYSTEM OVERVIEW
The CDB4226 evaluation board is designed to allow thorough evaluation of the CS4226 surround sound codec. Six RCA jacks allow input of up to three stereo signal sources to the analog input multiplexer of the CS4226, plus one RCA jack for a monaural auxiliary input. One of the stereo pairs can be selected for the stereo 20 bit ADCs, while the auxiliary input is sent to the mono 20-bit ADC. The CS4226 also has six 20-bit DACs, whose outputs are filtered, buffered, and routed to six RCA jacks. Digital audio S/PDIF signals can be input to the CS4226's S/PDIF receiver through optical and coaxial connectors. A CS8402A digital audio transmitter provides optical and coaxial S/PDIF outputs. Serial audio data I/O is provided by the AUX port and the DSP port. Both ports can be configured to operate with numerous interface formats. The CS4226 supports software control via the SPI and I2C interfaces. A DB-25 connector is provided to allow connection to the serial control port. PC software is provided which establishes an SPI interface using the PC's printer port. This software provides a means for the user to read and write the control registers on the CS4226. The CDB4226 schematic has been partitioned into 10 small schematics shown in Figures 3 through 12.
ANALOG INPUTS
The CS4226 is capable of switching between three stereo pairs of line level inputs, and is equipped with a mono auxiliary input. The desired input is selected by setting the AIS1/0 bits in the ADC Control Byte and the CSP bit in the AUX Port Control Byte (consult the CS4226 data sheet for details on the configuration registers). The seven analog inputs (AIN1L, AIN1R, AIN2L, AIN2R, AIN3L, AIN3R, and AINAUX) are low-pass filtered and buffered, as shown in Figures 4 and 5 (-3 dB at 200 kHz). The AC coupling caps (C56-C62) allow the input pins of the CS4226 to self-bias to approximately 2.3 Volts. A nominal amplitude of 1 Vrms to these inputs will achieve a full scale digital output from the A/D converters in the CS4226. All inputs are noninverting. AIN1L, AIN1R, and AINAUX are dedicated analog input connections to the CS4226. However, AIN2L, AIN2R, AIN3L, and AIN3R can also function as digital outputs (Figure 5). The output names are FREQ0, FREQ1, AUTODATA, and /AUDIO, respectively. When configured as outputs, these pins provide channel status information from the on-chip S/PDIF receiver (consult the CS4226 data sheet for details on pinout functionality). The status of these pins can be monitored with the LED's provided (D8-D9). The four jumpers HDR5-HDR8, defined in Table 1, are used in conjunction with the CSP bit in the Auxiliary Port Control Byte to configure these pins. When the CSP bit is a logic low, the pins become analog inputs. In this configuration, HDR5-HDR8 should be placed in the AIN position. When the CSP bit is a logic high, the pins become digital outputs; in this case HDR5-HDR8 should be placed in the CSOUT position. Note that the four jumpers should each be set to the same corresponding position. The CS4226 also supports a differential input mode in which the single-ended inputs AIN3L and AIN2L become differential inputs AINL+ and AINL-, respectively. Likewise, the single-ended
POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six binding posts as shown in Figure 3. +5 VA and AGND provide 5 Volt power to the CS4226. The +/-12 V binding posts provide power to the analog input and output buffers. The +5 VD and GND binding posts supply 5 Volt power to the digital section of the board. All power supply connections are equipped with transient suppression diodes and bulk filtering capacitors.
38
DS188DB1
CDB4226
JUMPER HDR5, HDR6, HDR7, HDR8 PURPOSE Sets the direction of AIN3R/AUDIO, AIN3L/AUTODATA, AIN2L/FREQ0, and AIN2R/FREQ1. All four jumpers must be set to the same position, and correspond with the CSP bit in AUX Port Control Byte. Selects the configuration for the XT pin on the DSP port. Jumper position must correspond with the DMS1/0 bits in the DSP Port Mode Byte and with the direction of the transceiver, U16. Routes S/PDIF datastream from RX_OPT to one of three S/PDIF receiver input pins on the CS4226, RX2, 3, or 4. Jumper position must correspond with the CS2/1/0 bits in the Clock Mode Byte. Tristates CLKOUT1 on AUX_HDR, allowing AUX_HDR to be compatible with 10-pin serial data connectors found on other Crystal CDB capture boards. POSITION FUNCTION SELECTED AIN Pins 9-12 on CS4226 are analog inputs (CSP=0). CSOUT Pins 9-12 on CS4226 are channel status outputs (CSP=1). XT is input to XTI. Y1 must be removed. U16 must be configured as input. XT is disconnected from XTI/XTO and is grounded through 47K resistor. XT outputs XTO clock from CS4226. U16 must be configured as output. Sends optical input to RX2 of CS4226. Sends optical input to RX3 of CS4226. Sends optical input to RX4 of CS4226. Configures board for AUX port input.
XT_SEL
XTIN XTAL XTOUT RX2 RX3 RX4 RX_AUXB
RX_SEL
CLK_SEL
CLKOFF CLKOUT1
Tristates CLKOUT1 buffer on U3. Enables CLKOUT1 buffer on U3.
Table 1. Jumper-selectable Options
inputs AIN2R and AIN1R become differential inputs AINR- and AINR+, respectively. Selection of the differential mode is made with the AIS1/0 bits in the ADC Control Byte. The balanced input configuration can be tested using special cables which have a male XLR connector on one end and a pair of RCA connectors on the other end.
ANALOG OUTPUTS
The six DAC outputs, AOUT1-AOUT6, are passed through a 2-pole Butterworth low-pass filter and are AC coupled, as shown in Figure 6 (-3 dB at 44.1 kHz). Each output will produce a nominal 1 Vrms output for a full scale digital input. Note that the filter outputs, OUT1-OUT6, are noninverting. The output filters in Figure 6 have additional resistor and capacitor sockets to accomodate a 3-pole Butterworth filter This may be useful if increased out-of-band noise filtering is desired.
The CS4226 provides a common mode biasing voltage of approximately 2.3 V on its CMOUT pin. The CDB4226 analog inputs and outputs are AC coupled, and hence CMOUT is not required on the input and output filter stages. Since other filter topologies may need a common mode bias voltage, a buffered version of CMOUT is available on the test point labeled CMOUTFO (Figure 4).
CLOCK CONFIGURATIONS
The timing on the board should be generated by a single clock source, with the DSP port and AUX port operating synchronously to the selected clock source. Operating the serial audio interfaces at clock frequencies which deviate from each other will cause the CS4226 to reset its data paths in an attempt to resynchronize. Potential clock sources are: 1) the recovered clock from the S/PDIF receiver on the CS4226,
DS188DB1
39
CDB4226
2) the LRCK or LRCKAUX inputs to the CS4226, 3) a 1 Fs, 256 Fs, 384 Fs, or 512 Fs crystal connected between XTI and XTO on the CS4226, or 4) a 1 Fs, 256 Fs, 384 Fs, or 512 Fs clock connected to XTI on the CS4226 from the XT clock line on the DSP port, DSP_HDR. The clock source is chosen by setting the Clock Source bits, CS2/1/0 in the Clock Mode Byte, and by configuring the XT_SEL jumper, defined in Table 1, to the appropriate position, as described below. inputs to the evaluation board. The PC software is used to set the DMS1/0 bits to 00 (LRCK and SCLK are inputs). Also, the software is used to set the direction of the bidirectional buffer, U16, so that XT, SCLK, and LRCK are buffered onto the board. Notice that when XT is used as an external master clock source for the board, the SCLK and LRCK lines cannot be outputs. SCLK and LRCK must be sourced externally.
DIGITAL INPUTS
The CS4226 can accept digital audio signals in either serial form or S/PDIF form. The CS2/1/0 bits in the Clock Mode Byte are used in conjunction with the RX_SEL jumper (defined in Table 1) to configure the board for serial or S/PDIF data sources.
XT_SEL Jumper and XT Clock Line
When the master clock for the board is derived from methods (1), (2), or (3), the XT_SEL jumper may be set to the XTAL position. This position disconnects the XT clock line on the DSP port (Figure 9) from the XTI/XTO clock and crystal pins of the CS4226 (Figure 7). In case (3), the XT line can be set up to output the XTO signal from the CS4226. This configuration makes a buffered version of the crystal clock frequency available on the DSP port. This is accomplished by setting XT_SEL to the XTOUT position, and by configuring the bidirectional clock lines, XT, SCLK, and LRCK, to be outputs. The PC software can be used to set the DMS 1/0 bits in the DSP Port Mode Byte to 01 or 10, making the clock lines outputs on the CS4226. The PC software also generates a control line called SP_BUF, which controls the direction of the bidirectional transceiver, U16 (Figure 8). Care must be taken to ensure that the DMS bit settings correspond to the direction set by the software control line. Details on the software are given in the last section of this datasheet. In case (4), the XT line can serve as the master clock source for the CDB4226. To configure the board in this manner, set the XT_SEL jumper to the XTIN position. Additionally, the XT, SCLK, and LRCK lines on the DSP port must be configured as
40
Serial Input Interface
Serial data can be received through the AUX port header, AUX_HDR (Figure 8), which provides access to the AUX port of the CS4226. The four clock and data lines on AUX_HDR are defined in Table 2. The CS4226 will accept serial data through the AUX port by setting the CS2/1/0 bits in the Clock Mode Byte to 0, 1, 2, or 3 (hex), and by moving the RX_SEL jumper to the RX_AUXB position. Notice that the LRCLKAUX and SCLKAUX lines on the AUX port are bidirectional. The AMS1/0 bits in the Auxiliary Port Mode Byte determine the direction of the LRCLKAUX and SCLKAUX lines. The PC software generates a control line called AUX_BUF, which controls the direction of the bidirectional transceiver, U23 (Figure 8). Care must be taken to ensure that the AMS bits correspond to the direction set by the software control line. Details on the software are given in the last section of this datasheet. A buffered version of CLKOUT, called CLKOUT1, is available on AUX_HDR. CLKOUT frequencies of 1 Fs, 256 Fs, 384 Fs, and 512 Fs can be selected using the CO1/0 bits in the Clock Mode
DS188DB1
CDB4226
CONNECTOR NAME +5 VA +5 VD +/- 12 V AGND GND AIN1L, AIN1R AIN2L, AIN2R AIN3L, AIN3R AINAUX OUT1 - OUT6 RX_DIG RX_OPT 8402_DIG 8402_OPT DATAUX LRCLKAUX, SCLKAUX CLKOUT1 SCL/CCLK1 SDA/CDOUT1 SDIN1, SDIN2, SDIN3 XT CLKOUT LRCK, SCLK SDOUT1, SDOUT2 PC CONN CONNECTOR TYPE binding post binding post binding post binding post binding post RCA RCA RCA RCA RCA RCA Toslink RCA Toslink header (AUX_HDR) header (AUX_HDR) header (AUX_HDR) header (DSP_HDR) header (DSP_HDR) header (DSP_HDR) header (DSP_HDR) header (DSP_HDR) header (DSP_HDR) header (DSP_HDR) DB-25 INPUT / OUTPUT input input input input input inputs inputs inputs input outputs input input output output input inputs/outputs output input bidirectional inputs input/output output inputs/outputs outputs inputs/outputs SIGNAL PRESENT +5 Volts for analog section +5 Volts for digital section +/- 12 Volts for analog input and output buffers analog ground connection from power source digital ground connection from power source left and right channel analog inputs, 1st stereo pair left and right channel analog inputs, 2nd stereo pair left and right channel analog inputs, 3rd stereo pair auxiliary analog input six buffered and filtered DAC output channels coaxial input to RX1 of CS4226 S/PDIF receiver optical input to RX2, 3, or 4 of CS4226 S/PDIF receiver CS8402A digital output via transformer CS8402A digital output via optical transmitter AUX port serial data input I/O for AUX port serial and left/right clocks buffered CLKOUT from CS4226 serial control clock for I2C interface control data I/O line for I2C interface DSP port serial data inputs DSP port XTI input access, or buffered XTO from CS4226 buffered CLKOUT from CS4226 I/O for DSP port serial and left/right clocks DSP port serial data outputs DB-25 connector to PC for SPI/I2C control port signals
Table 2. System Connections
Byte. This clock line is useful for synchronizing external A/D converters or other peripheral components. CLKOUT1 can be tristated by selecting the position of the CLK_SEL jumper, defined in Table 1. This feature may be useful in interfacing other Crystal evaluation boards (CDB5330A and CDB5334/35 for example) to the CDB4226, as it prevents a drive contention on the MCLK output of these boards.
S/PDIF Input Interface
The optical and coaxial digital inputs labeled RX_OPT and RX_DIG (Figure 8) allow access to
the on-chip S/PDIF receiver, which can receive and decode one of four S/PDIF input sources. Setting the CS2/1/0 bits in the Clock Mode Byte to 4, 5, 6, or 7 (hex) will configure the CS4226 to choose RX1, RX2, RX3, or RX4, respectively, as the S/PDIF input source. The coaxial input, RX_DIG, is dedicated to the RX1 input on the CS4226. The optical input, RX_OPT, can be routed to one of the three other S/PDIF receiver input pins by using the RX_SEL jumper. Setting RX_SEL to the RX2, RX3, or RX4 position will route the S/PDIF data from the optical input to the RX2, RX3, or RX4 pin of the codec.
DS188DB1
41
CDB4226
DSP PORT
The DSP port header, DSP_HDR, provides access to the DSP port of the CS4226. The eleven clock, control, and data lines are defined in Table 2. The XT, SCLK, and LRCK lines can be inputs or outputs, and their I/O configuration is defined in the "Clock Configuration" section above. CLKOUT, SDOUT1, and SDOUT2 are buffered outputs from the CS4226. The serial data input lines, SDIN1, 2, and 3, provide external access to the SDIN1, 2, and 3 pins of the CS4226. The I2C interface lines, labeled SDA/CDOUT1 and SCL/CCLK1, allow configuration of the CS4226 registers without having to use the PC connector, PC CONN. The Altera EPM7032 programmable logic device (PLD), shown in Figure 11, is used to route serial audio data in several ways on the board. The switches on S2 labeled SDIN_M2/M1/M0 (Figure 11) select the input to the SDIN1, 2 and 3 pins of the CS4226. The various routing schemes are defined in Table 3. There are seven loopback configurations which are selected by setting SDIN_M2/M1/M0 to 0-6 (hex). To access the SDIN pins on the codec from the DSP port header, SDIN_M2/M1/M0 should be set to 7 (hex). The DIP switches SW1 and S2 (Figure 9) configure the PLD to adjust the clock and data outputs of the CS4226 to the format requirements of the CS8402A. The functionality of each switch is described below.
CS8402A MCLK Generation
The CLKOUT signal of the CS4226 can be 1 Fs, 256 Fs, 384 Fs, or 512 Fs. The CS8402A requires a master clock frequency of 128 Fs to operate. When CLKOUT is 1 Fs, the CS8402A will be inoperable. However, to accomodate the other possible frequencies of CLKOUT, the evaluation board can be configured to divide CLKOUT by 2, 3, or 4 to generate a 128 Fs master clock for the transmitter. The switches on SW1 labeled MCLK_S1 and MCLK_S0 select the degree of clock division as defined in Table 3.
CS8402A Format Selection
The five switches on SW1 and S2 labeled SP_RISING, SP_L_RB, BITS1, BITS0, and I2S are used to select the correct digital interface format for the CS8402A. These switches are defined in Table 3. Their settings must correspond with the DSCK and DDF2/1/0 bits in the DSP Port Mode Byte register. Table 4 shows which DSP Port Mode Byte settings the CS8402A can support for S/PDIF transmission. All other settings not listed in the table are not valid.
S/PDIF OUTPUT
A CS8402A digital audio transmitter, shown in Figure 9, allows serial data from either SDOUT1 or SDOUT2 to be transmitted in S/PDIF form through an optical transmitter (8402_OPT) and through an RCA connector (8402_DIG). The transmitter provides a convenient way to evaluate the performance of the A/D converters on the CS4226.
SDOUTx Output Selection
The switch on S2 labeled SDOUT_M0 selects the source of data to the CS8402A. A logic low selects SDOUT1 for transmission, and a logic high selects SDOUT2.
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SW1 SWITCH # 6, 5 Comment Divides CLKOUT to generate MCLK_8402 for CS8402A transmitter. Generates a 128 Fs clock when CLKOUT = 256 Fs (CO = 0). RESERVED Generates a 128 Fs clock when CLKOUT = 384 Fs (CO = 1). Generates a 128 Fs clock when CLKOUT = 512 Fs (CO = 2). Selects SCLK valid data edge. This bit must agree with DSCK bit in DSP Port Mode Byte. 0 Data is clocked into CS8402A on falling edge of SCLK (DSCK = 1). 1 Data is clocked into CS8402A on rising edge of SCLK (DSCK = 0). SP_L_RB Selects left or right justified data. This bit must agree with DDF bits in DSP Port Mode Byte. 0 Serial data lines are right justified (DDF = 0,1,2). 1 Serial data lines are left justified (DDF 0,1,2). BITS1, BITS0 Selects bits of resolution. These bits must agree with DDF bits in DSP Port Mode Byte. 00 16 bits (DDF = 2) 01 18 bits (DDF = 1) 10 20 bits (DDF = 0, 3) 11 RESERVED 0 = closed, 1 = open Comment 2 Selects I2S compatible mode. This bit must agree with DDF bits in IS DSP Port Mode Byte. 0 I2S mode off (DDF 4). 1 I2S mode on (DDF = 4). SDOUT_M0 Selects the source of data to the CS8402A. 0 SDOUT1 from CS4226 is routed to SDATA pin of CS8402A. 1 SDOUT2 from CS4226 is routed to SDATA pin of CS8402A. SDIN_M2, SDIN_M1, Selects the source of data to SDIN1, 2, and 3 on the CS4226. Choices SDIN_M0 are SDOUT lines from the CS4226, SDIN lines from DSP_HDR, or zeros. 000 SDOUT1 => SDIN1, 0 => SDIN2, 0 => SDIN3 001 0 => SDIN1, SDOUT1 => SDIN2, 0 => SDIN3 010 0 => SDIN1, 0 => SDIN2, SDOUT1 => SDIN3 011 SDOUT1 => SDIN1, SDOUT1 => SDIN2, SDOUT1 => SDIN3 100 SDOUT2 => SDIN1, SDOUT2 => SDIN2, SDOUT2 => SDIN3 101 SDOUT1 => SDIN1, SDOUT1 => SDIN2, SDOUT2 => SDIN3 110 SDOUT1 => SDIN1, SDOUT2 => SDIN2, SDOUT2 =>SDIN3 111 SDIN1_HDR =>SDIN1, SDIN2_HDR =>SDIN2, SDIN3_HDR =>SDIN3 Table 3. DIP Switch Definitions 0 = closed, 1 = open MCLK_S1, MCLK_S0 00 01 10 11 SP_RISING
4
3
2, 1
S2 SWITCH # 5
4
3, 2, 1
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DSP Port Mode Byte (hex)
1 = open, 0 = closed, X = don't care, N/A = not available Descriptor DCK1-DCK0 = 00, 01, or 11 => 128, 48, or 64 bit clocks per Fs period. CS4226 slave, valid data on SCLK rising edge, right-justified, 18 bit CS4226 slave, valid data rising edge, right-justified, 16 bit CS4226 slave, valid data rising edge, left-justified, 20 bit in, 24 bit out CS4226 slave, valid data rising edge, I2S, 20 bit in, 24 bit out CS4226 slave, valid data on SCLK falling edge, right-justified, 18 bit CS4226 slave, valid data falling edge, right-justified, 16 bit CS4226 slave, valid data falling edge, left-justified, 20 bit in, 24 bit out CS4226 slave, valid data falling edge, I2S, 20 bit in, 24 bit out CS4226 master burst, valid data on SCLK rising edge, right-justified, 18 bit CS4226 master burst, valid data rising edge, right-justified, 16 bit CS4226 master burst, valid data rising edge, left-justified, 20 bit in, 24 bit out CS4226 master burst, valid data rising edge, I2S, 20 bit in, 24 bit out CS4226 master burst, valid data on SCLK falling edge, right-justified, 18 bit CS4226 master burst, valid data falling edge, right-justified, 16 bit CS4226 master burst, valid data falling edge, left-justified, 20 bit in, 24 bit out CS4226 master burst, valid data falling edge, I2S, 20 bit in, 24 bit out CS4226 master nonburst, valid data on SCLK rising edge, right-justified, 18 bit CS4226 master nonburst, valid data rising edge, right-justified, 16 bit CS4226 master nonburst, valid data rising edge, left-justified, 20 bit in, 24 bit out CS4226 master nonburst, valid data rising edge, I2S, 20 bit in, 24 bit out CS4226 master nonburst, valid data on SCLK falling edge, right-justified, 18 bit CS4226 master nonburst, valid data falling edge, right-justified, 16 bit CS4226 master nonburst, valid data falling edge, left-justified, 20 bit in, 24 bit out CS4226 master nonburst, valid data falling edge, I2S, 20 bit in, 24 bit out DCK1-DCK0 = 10 =>32 bit blocks per Fs period (all formats default to 16 bits) CS4226 slave, valid data on SCLK rising edge, right-justified,16 bit CS4226 slave, valid data rising edge, left-justified, 16 bit CS4226 slave, valid data rising edge, I2S, 16 bit CS4226 slave, valid data on SCLK falling edge, right-justified, 16 bit CS4226 slave, valid data falling edge, left-justified, 16 bit CS4226 slave, valid data falling edge, I2S, 16 bit CS4226 master burst, valid data on SCLK rising edge, right-justified, 16 bit CS4226 master burst, valid data rising edge, left-justified, 16 bit CS4226 master burst, valid data rising edge, I2S, 16 bit CS4226 master burst, valid data on SCLK falling edge, right-justified, 16 bit CS4226 master burst, valid data falling edge, left-justified, 16 bit CS4226 master burst, valid data falling edge, I2S, 16 bit CS4226 master nonburst, valid data on SCLK rising edge, right-justified, 16 bit CS4226 master nonburst, valid data rising edge, left-justified, 16 bit CS4226 master nonburst, valid data rising edge, I2S, 16 bit CS4226 master nonburst, valid data on SCLK falling edge, right-justified, 16 bit CS4226 master nonburst, valid data falling edge, left-justified, 16 bit CS4226 master nonburst, valid data falling edge, I2S, 16 bit
SW1: S2: #5 #2, #1 SP_RISING SP_L_RB BITS1/ I2S BITS0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 X 0 0 1 X 0 0 1 X 0 0 1 X 0 0 1 X 0 0 1 X 0 1 X 0 1 X 0 1 X 0 1 X 0 1 X 0 1 X 01 00 10 XX 01 00 10 XX 01 00 10 XX 01 00 10 XX 01 00 10 XX 01 00 10 XX 00 XX XX 00 00 XX 00 00 XX 00 00 XX 00 00 XX 00 00 XX 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1
SW1: #4
SW1: #3
01, 41, C1 02, 42, C2 03, 43, C3 04, 44, C4 09, 49, C9 0A, 4A, CA 0B, 4B, CB 0C, 4C, CC 11, 51, D1 12, 52, D2 13, 53, D3 14, 54, D4 19, 59, D9 1A, 5A, DA 1B, 5B, DB 1C, 5C, DC 21, E1 22, E2 23, E3 24, E4 29, E9 2A, EA 2B, EB 2C, EC 80, 81, 82 83 84 88, 89, 8A 8B 8C 90, 91, 92 93 94 98, 99, 9A 9B 9C A0, A1, A2 A3 A4 A8, A9, AA AB AC
Table 4. DSP Port Formats Supported by CS8402A Transmitter
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SPI CONTROL PORT SOFTWARE
The SPI/I2C port can be accessed through the DB25 connector, PC CONN. Software is provided which allows reading and writing of the CS4226 control port registers with a PC using the SPI format. The supplied cable should be attached between PC CONN and the PC parallel port. This routine returns the value located in the register pointed to by . The value is in hex and the value returned is in hex. WRSPI This routine writes the into the register pointed to by . Both values are in hex. DUMPSPI This routine dumps the value of all the registers starting at up to register 25. RDPSI, WRSPI, and DUMPSPI have an optional argument "-pXX", defined in Table 5. This argument is used to set the direction of the bidirectional transceivers, U23 (Figure 8) and U16 (Figure 9). The "-pXX" argument must be sent at least once after powerup to configure the evaluation board to recognize whether the AUX port and DSP port are in master mode (clock lines are outputs) or in slave mode (clock lines are inputs). The "-pXX" argument should be set with consideration of setting the DMS bits in the DSP Port Mode Byte and the AMS bits in the Auxiliary Port Mode Byte.
Software Description
Four C programs have been compiled to operate under MS-DOS. These programs can be run directly from the floppy disk provided. A brief description of the supplied routines is given. To see a full argument list for each routine, simply type the command with no arguments. RSTSPI Send a brief reset to the board. This is the same as depressing the /PDN switch. RDSPI
Optional Argument -p00 -p08 -p10 -p18 -e
Description CS4226 AUX port is master, DSP port is master (User must set AMS=2, DMS=2) CS4226 AUX port is master, DSP port is slave (User must set AMS=2, DMS=0) CS4226 AUX port is slave, DSP port is master (User must set AMS=0, DMS=2) CS4226 AUX port is slave, DSP port is slave (User must set AMS=0, DMS=0) specifies an ending register on DUMPSPI
Table 5. Optional Software Switch Statements for RDSPI, WRSPI, and DUMPSPI commands
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CDB4226
Pre-Configured Setups
For ease of implementation, batch files are provided along with the required jumper and dip switch settings for two modes of operation. Choice of operation mode is based primarily on the desired source of the data. All jumper settings not mentioned remain unchanged.
DIP Switch Settings:
LOCATED ON S2 SDIN_M0 - 1 = >OPEN SDIN_M1 - 1 = >OPEN SDIN_M2 - 0 = >CLOSED SDOUT_M0 -0 = >CLOSED I2S - 0 = >CLOSED LOCATED ON SW1 BITS0 - 0 = >CLOSED BITS1 -1 = > OPEN SP_L_RB - 1 = >OPEN SP_RISING - 0 = >CLOSED MCLK_S0 - 0 = >CLOSED MCLK_S1 - 0 = >CLOSED
1: Receiver Mode
The clock source is a recovered clock from the S/PDIF coax input, RX_DIG. Recovered data is transmitted by the CS8402A. Additionally, SDOUT1 data is looped back to the DACs. Type "powuprx1" at the appropriate prompt to run the batch file for this mode of operation.
Signal Flow:
Jumper Settings:
XT_SEL - XTAL RX_SEL - RX2, RX3 or RX4 HRDR5,6,7,8 - CSOUT
Batch File:
POWUPRX1.BAT
2: Crystal mode
The clock source is a crystal (Y1). Stereo ADC output data is transmitted by the CS8402A. SDOUT1 data is looped back to the DACs. The stereo signal is applied to stereo pair 1 on the evaluation board (AIN1L/R). Type "powupxtl" at the appropriate prompt to run the batch file for this mode of operation.
Figure 1. CDB4226 in Receiver Mode
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Signal Flow: DIP Switch Settings:
LOCATED ON S2 SDIN_M0 - 1 = >OPEN SDIN_M1 - 1 = >OPEN SDIN_M2 - 0 = >CLOSED SDOUT_M0 - 0 = >CLOSED I2S - 0 = >CLOSED LOCATED ON SWI BITS0 - 0 = >CLOSED BITS1 - 1 = >OPEN SP_L_RB - 1 = >OPEN SP_RISING - 0 = >CLOSED MCLK_S0 - 0 = >CLOSED MCLK_S1 - 0 = >CLOSED
JumperSettings:
HRDR5,6,7,8 - AIN XT_SEL - XTAL
Batch File:
Figure 2. CDB4226 in Crystal Mode
POWUPXTL.BAT
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CDB4226
Figure 3. Power Supply and Bulk Filtering
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Figure 4. Dedicated Analog Inputs
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Figure 5. Analog Inputs/Channel Status Outputs with LED Indicators
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Figure 6. Analog Outputs
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Figure 7. CS4226
CDB4226
Figure 8. AUX Port and S/PDIF Inputs
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CDB4226
Figure 9. DSP Port
Figure 10. CS8402A Digital Audio Transmitter
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Figure 11. Altera PLD and DIP Switches
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Figure 12. SPI/I2C Control Port Interface
CDB4226
Figure 13. CDB4226 Rev. B Silkscreen (not to scale)
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CDB4226
Figure 14. CDB4226 Rev. B Component Side (not to scale)
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Figure 15. CDB4226 Rev. B Solder Side (not to scale)
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